The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Jan. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Tainan, TW;

Tsung-Han Tsai, Miaoli, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01);
Abstract

A semiconductor device structure includes a first MOSFET device disposed at a first region of a semiconductor substrate, the first MOSFET device comprises a bulk semiconductor layer contacting the semiconductor substrate, and the bulk semiconductor layer has a first height, a first gate structure disposed over the bulk semiconductor layer, and first S/D regions disposed in the bulk semiconductor layer on opposite sides of the first gate structure; a second MOSFET device disposed at a second region of the semiconductor substrate, the second MOSFET device comprises a semiconductor layer disposed over the semiconductor substrate, and the semiconductor layer has a second height different than the first height, a second gate structure disposed over the semiconductor layer, and second S/D regions disposed in the semiconductor layer on opposite sides of the second gate structure; an insulator between and in contact with the semiconductor substrate and semiconductor layer; and a spacer layer isolating the first and second MOSFET devices, and a portion of the spacer layer is disposed between and in contact with the insulator layer and bulk semiconductor layer.


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