The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Dec. 09, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Kuan-Hsiang Mao, Kaohsiung, TW;

Wen Hung Huang, Kaohsiung, TW;

Che Ming Fang, Kaohsiung, TW;

Yufu Liu, Kaohsiung, TW;

Assignee:

NXP B.V, Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/78 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/05558 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.


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