The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Mar. 24, 2021
Applicant:

Shenzhen Pango Microsystems Co.,ltd., Shenzhen, CN;

Inventors:

Shiyjun Zhao, Shenzhen, CN;

Puxia Liu, Shenzhen, CN;

Qipan Fu, Shenzhen, CN;

Assignee:

SHENZHEN PANGO MICROSYSTEMS CO., LTD., Guangdong Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318544 (2013.01); G01R 31/318569 (2013.01);
Abstract

A boundary scan test method is used to test connectivity of a pad having a direct connection to user logic. The method comprises the following steps: configuring an FPGA to enter a test mode; generating by means of user logic, a boundary scan chain for a boundary scan test; loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a pad to be tested for connectivity; sending, via a TDI port, a first test vector to the pad; performing the boundary scan test, and loading an EXTEST instruction to the device having the pad; and removing first response data from a TDO port, and performing response analysis and fault diagnosis.


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