The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2024
Filed:
Jul. 26, 2022
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0274 (2013.01); H01L 21/0337 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31122 (2013.01); H01L 21/3212 (2013.01); H01L 21/32136 (2013.01); H01L 21/76832 (2013.01); H01L 29/4236 (2013.01); H01L 29/66553 (2013.01); H01L 29/7851 (2013.01); H01L 29/7848 (2013.01);
Abstract
A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.