The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Aug. 09, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Ming Chang, Zhubei, TW;

Chih-Ming Lai, Hsinchu, TW;

Ru-Gun Liu, Zhubei, TW;

Tsai-Sheng Gau, HsinChu, TW;

Chung-Ju Lee, Hsinchu, TW;

Tien-I Bao, Dayuan Township, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/321 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/76807 (2013.01); H01L 21/76808 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 21/76885 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 21/76834 (2013.01); H01L 21/76883 (2013.01); H01L 2221/1063 (2013.01);
Abstract

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.


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