The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Dec. 09, 2022
Applicants:

Inventec (Pudong) Technology Corporation, Shanghai, CN;

Inventec Corporation, Taipei, TW;

Inventors:

Chang-Qing Mu, Shanghai, CN;

Yuan Sang, Shanghai, CN;

Xue-Shan Han, Shanghai, CN;

Assignees:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318533 (2013.01); G01R 31/318536 (2013.01); G01R 31/318572 (2013.01); G01R 31/318597 (2013.01);
Abstract

A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.


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