The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Jan. 13, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Hsuan Liu, Tainan, TW;

Chiang-Ming Chuang, Changhua, TW;

Chih-Ming Lee, Tainan, TW;

Kun-Tsang Chuang, Miaoli County, TW;

Hung-Che Liao, Tainan, TW;

Chia-Ming Pan, Tainan, TW;

Hsin-Chi Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/50 (2023.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/10 (2023.01); H10B 41/30 (2023.01); H10B 41/42 (2023.01); H10B 41/47 (2023.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/32135 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H10B 41/10 (2023.02); H10B 41/42 (2023.02); H10B 41/47 (2023.02);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.


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