The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

May. 24, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Lars Liebmann, Albany, NY (US);

Jeffrey Smith, Clifton Park, NY (US);

Daniel Chanemougame, Albany, NY (US);

Paul Gutwin, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 23/528 (2013.01); H01L 23/53271 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.


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