The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Jul. 12, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Shu Wu, Taoyuan, TW;

Shu-Uei Jang, Hsinchu, TW;

Wei-Yeh Tang, Taoyuan, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

An-Chyi Wei, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/31116 (2013.01); H01L 21/76865 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/161 (2013.01); H01L 21/823412 (2013.01);
Abstract

A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.


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