The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2024
Filed:
Oct. 16, 2020
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Erik A. Verduijn, Leuven, BE;
Ulrich Karl Klostermann, Munich, DE;
Ulrich Welling, Aschheim/Dornach, DE;
Jiuzhou Tang, Aschheim/Dornach, DE;
Hans-Jürgen Stock, Dachau, DE;
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/00 (2006.01); G06F 30/23 (2020.01); G03F 7/004 (2006.01); G06F 17/15 (2006.01);
U.S. Cl.
CPC ...
G03F 7/7065 (2013.01); G03F 7/0045 (2013.01); G06F 17/15 (2013.01); G06F 30/23 (2020.01);
Abstract
A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.