The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Mar. 24, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Hung Cho Wang, Taipei, TW;

Sheng-Chang Chen, Hsinchu County, TW;

Sheng-Huang Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.


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