The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Feb. 24, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hidehiro Fujiwara, Hsin-Chu, TW;

Haruki Mori, Hsinchu, TW;

Wei-Chang Zhao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01); G06F 7/544 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 7/5443 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 7/12 (2013.01);
Abstract

A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.


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