The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

May. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Wei Peng, Hsinchu, TW;

Chih-Min Hsiao, Hsinchu, TW;

Ching-Hsu Chang, Hsinchu, TW;

Jiann-Tyng Tzeng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/522 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G03F 1/42 (2012.01); H01L 23/528 (2006.01); G06F 30/31 (2020.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G03F 1/42 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/31 (2020.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01);
Abstract

A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.


Find Patent Forward Citations

Loading…