The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Jul. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chang-Yun Chang, Taipei, TW;

Bone-Fong Wu, Hsinchu, TW;

Ming-Chang Wen, Kaohsiung, TW;

Ya-Hsiu Lin, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/027 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/0217 (2013.01); H01L 21/02156 (2013.01); H01L 21/31111 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 21/0274 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/324 (2013.01); H01L 21/76224 (2013.01); H01L 29/6656 (2013.01);
Abstract

A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.


Find Patent Forward Citations

Loading…