The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Dec. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Dian-Sheg Yu, Hsinchu, TW;

Ren-Fen Tsui, Taipei, TW;

Jhon Jhy Liaw, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/76802 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 27/0203 (2013.01); H01L 29/0847 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 21/76814 (2013.01); H01L 21/76897 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H10B 10/18 (2023.02);
Abstract

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.


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