The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Sep. 10, 2021
Applicant:

Sj Semiconductor (Jiangyin) Corporation, Jiangyin, CN;

Inventors:

Yenheng Chen, Jiangyin, CN;

Chengchung Lin, Jiangyin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 33/62 (2010.01); H01L 33/54 (2010.01); H01L 23/42 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3135 (2013.01); H01L 23/367 (2013.01); H01L 23/42 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/94 (2013.01); H01L 33/54 (2013.01); H01L 33/62 (2013.01); H01L 2224/16225 (2013.01); H01L 2933/005 (2013.01);
Abstract

The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.


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