The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Mar. 06, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Zhenlei Shen, Milpitas, CA (US);

Tingjun Xie, Milpitas, CA (US);

Zhenming Zhou, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/42 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2029/0407 (2013.01);
Abstract

A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.


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