The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Apr. 22, 2021
Applicant:

Globalfoundries Dresden Module One Limited Liability Company & Co. KG, Dresden, DE;

Inventors:

Tarek Ali, Dresden, DE;

Konstantin H. J. Mertens, Dresden, DE;

Maximilian W. Lederer, Dresden, DE;

David J. Lehninger, Dresden, DE;

Konrad Seidel, Dresden, DE;

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H10B 53/30 (2023.01); H01L 49/02 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); H01L 28/60 (2013.01); H01L 29/516 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02);
Abstract

Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.


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