Techniques for precharging a memory cell

Abstract

Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.