The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Nov. 08, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Liang Chen, Wuhan, CN;

Cheng Gan, Wuhan, CN;

Xin Wu, Wuhan, CN;

Wei Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/404 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/24 (2013.01); G11C 11/404 (2013.01); H01L 28/40 (2013.01); H10B 12/395 (2023.02);
Abstract

In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.


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