The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Dec. 23, 2021
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Chien-Ming Lu, Kaohsiung, TW;

Fu-Che Lee, Taichung, TW;

Chien-Cheng Tsai, Kaohsiung, TW;

Chiu-Fang Hsu, Miaoli County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H10B 12/053 (2023.02); H01L 21/02164 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 29/0653 (2013.01); H10B 12/34 (2023.02); H01L 21/02238 (2013.01); H10B 12/488 (2023.02);
Abstract

A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.


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