The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Apr. 12, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Han-Wen Chen, Cupertino, CA (US);

Steven Verhaverbeke, San Francisco, CA (US);

Giback Park, San Jose, CA (US);

Kyuil Cho, Santa Clara, CA (US);

Kurtis Leschkies, San Jose, CA (US);

Roman Gouk, San Jose, CA (US);

Chintan Buch, Santa Clara, CA (US);

Vincent Dicaprio, Pleasanton, CA (US);

Bernhard Stonas, Hayward, CA (US);

Jean Delmas, Santa Clara, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01);
Abstract

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.


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