The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Dec. 02, 2020
Applicant:

Cambridge Electronics, Inc., Cambridge, MA (US);

Inventors:

Bin Lu, Watertown, MA (US);

Dongfei Pei, Waban, MA (US);

Xiabing Lou, Belmont, MA (US);

Assignee:

Finwave Semiconductor, Inc., Belmont, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/2003 (2013.01); H01L 29/66712 (2013.01);
Abstract

This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.


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