The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Feb. 01, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Tomoharu Tanaka, Yokohama, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/225 (2013.01); G11C 16/3445 (2013.01);
Abstract

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.


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