IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11869893 B1

PDFFull Text
Date of Patent:
Jan. 09, 2024

Filed:

Oct. 27, 2021

Stacked field effect transistor with wrap-around contacts

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Chun-Chen Yeh, Danbury, CT (US);

Alexander Reznicek, Troy, NY (US);

Dechao Guo, Niskayuna, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Kimberly Zillig

Primary Examiner:

Joseph C Nicely

Assistant Examiner:

Lamont B Koo

Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02532 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/165 (2013.01); H01L 29/41758 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01);
Abstract

Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.

Find Patent Forward Citations

Loading…