The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

May. 24, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ralf Siemieniec, Villach, AT;

Dethard Peters, Hoechstadt, DE;

Roland Rupp, Lauf, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 29/45 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/7685 (2013.01); H01L 24/45 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05179 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05672 (2013.01); H01L 2224/05679 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01);
Abstract

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.


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