The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Dec. 02, 2021
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Joshua David Tygert, Seneca, PA (US);

Jonathan R. Fales, Finksburg, MD (US);

Rwik Sengupta, Austin, TX (US);

Timothy H. Pylant, La Grange, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01);
Abstract

Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.


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