The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Mar. 30, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Hung Yeh, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/08 (2006.01); H02H 1/00 (2006.01);
U.S. Cl.
CPC ...
H02H 3/08 (2013.01); H02H 1/0007 (2013.01);
Abstract

An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.


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