The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Nov. 18, 2021
Applicants:

Global Unichip Corporation, Hsinchu, TW;

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Ju Chang, Hsinchu, TW;

Jia-Liang Chen, Hsinchu, TW;

Chun-Hong Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/5383 (2013.01);
Abstract

An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.


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