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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11856854 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Sep. 02, 2021

Mram device structures and method of fabricating the same

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Feng Yin, Hsinchu County, TW;

Min-Kun Dai, Hsinchu, TW;

Chien-Hua Huang, Miaoli County, TW;

Chung-Te Lin, Tainan, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Caleb E Henry

Int. Cl.
CPC ...
H10N 50/01 (2023.01); G11C 11/16 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); G11C 11/161 (2013.01); H01L 21/7684 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02);
Abstract

Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

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