The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Chern-Yow Hsu, Chu-Bei, TW;

Chen-Jong Wang, Hsin-Chu, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Shih-Chang Liu, Alian Township, TW;

Xiaomeng Chen, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H10B 12/09 (2023.02); H01L 21/76877 (2013.01); H01L 28/90 (2013.01); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H10B 12/03 (2023.02);
Abstract

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.


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