The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Apr. 26, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chiu-Hsiang Chen, Hsinchu County, TW;

Shih-Chun Huang, Hsinchu, TW;

Yung-Sung Yen, New Taipei, TW;

Ru-Gun Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 27/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); G06F 30/392 (2020.01); H01L 21/0274 (2013.01); H01L 21/308 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 27/0207 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A method for fabricating a semiconductor device is provided. The method includes forming an alignment mark in a material layer, wherein the alignment mark has a step sidewall in the material layer, and the step sidewall of the alignment mark has a floor surface portion; forming a feature material over the material layer; and performing a planarization process at least on the feature material, wherein the planarization process stops at a level higher than the floor surface portion of the step sidewall of the alignment mark.


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