The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Aug. 08, 2022
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Tsmc Nanjing Company Limited, Nanjing, CN;

Inventors:

Yi-Lin Chuang, Taipei, TW;

Shi-Wen Tan, Nanjing, CN;

Song Liu, Nanjing, CN;

Shih-Yao Lin, Hsinchu, TW;

Wen-Yuan Fang, Nanjing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/392 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/373 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01);
Abstract

A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.


Find Patent Forward Citations

Chuang, Yi-Lin. (2023). Method for optimizing floor plan for an integrated circuit (U.S. Patent No. 11853675). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11853675

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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