The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Jun. 30, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Bo-Hsun Pan, New Taipei, TW;

Chien-Chang Li, New Taipei, TW;

Hung-Yu Chou, Taipei, TW;

Shawn Martin O'Connor, McKinney, TX (US);

Byron Lovell Williams, Plano, TX (US);

Jeffrey Alan West, Dallas, TX (US);

Zi-Xian Zhan, New Taipei, TW;

Sheng-Wen Huang, Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 23/4952 (2013.01); H01L 23/49575 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/45644 (2013.01); H01L 2224/45664 (2013.01); H01L 2224/48138 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48453 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/48481 (2013.01); H01L 2224/85035 (2013.01); H01L 2224/85051 (2013.01); H01L 2924/182 (2013.01);
Abstract

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.


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