The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Oct. 15, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Youquan Yu, Hefei, CN;

Gongyi Wu, Hefei, CN;

Shiran Zhang, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76224 (2013.01); H01L 21/76835 (2013.01); H01L 21/76843 (2013.01); H10B 12/488 (2023.02); H10B 12/09 (2023.02);
Abstract

Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.


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