The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jan. 03, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Meng-Sheng Chang, Hsinchu County, TW;

Yao-Jen Yang, Hsinchu County, TW;

Shao-Yu Chou, Hsinchu County, TW;

Yih Wang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 7/24 (2006.01); G11C 8/14 (2006.01); G11C 17/18 (2006.01); G06F 21/79 (2013.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G11C 17/16 (2013.01); G06F 12/14 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2013.01); G11C 8/14 (2013.01); G11C 17/18 (2013.01);
Abstract

A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.


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