The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Apr. 15, 2022
Applicant:

Asml Netherlands B.v., Veldhoven, NL;

Inventors:

Wei Fang, Milpitas, CA (US);

Lingling Pu, San Jose, CA (US);

Assignee:

ASML Netherlands B.V., Veldhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/33 (2017.01); G06T 7/73 (2017.01); G06T 7/13 (2017.01); G06T 7/00 (2017.01); H01L 21/67 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06T 7/337 (2017.01); G06T 7/001 (2013.01); G06T 7/13 (2017.01); G06T 7/74 (2017.01); H01L 21/67288 (2013.01); H01L 22/12 (2013.01); G06T 2207/10061 (2013.01); G06T 2207/30148 (2013.01);
Abstract

A method for aligning a wafer image with a reference image, comprising: searching for a targeted reference position on the wafer image for aligning the wafer image with the reference image; and in response to a determination that the targeted reference position does not exist: defining a current lock position and an area that encloses the current lock position on the wafer image; computing an alignment score of the current lock position; comparing the alignment score of the current lock position with stored alignment scores of positions previously selected in relation to aligning the wafer image with the reference image; and aligning the wafer image with the reference image based on the comparison.


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