The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Sep. 13, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Fu Chuang, Changhua County, TW;

Hsiu-Han Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/47 (2023.01); H10B 41/46 (2023.01); H10B 41/44 (2023.01);
U.S. Cl.
CPC ...
H10B 41/47 (2023.02); H10B 41/46 (2023.02); H10B 41/44 (2023.02);
Abstract

A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.


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