The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 02, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu, TW;

Fu-Hsiang Su, Zhubei, TW;

Ke-Jing Yu, Kaohsiung, TW;

Chih-Hong Hwang, New Taipei, TW;

Jyh-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/486 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H01L 29/41791 (2013.01); H01L 29/4232 (2013.01); H01L 29/66795 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.


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