The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Aug. 06, 2021
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Debraj Guhabiswas, Berkeley, CA (US);

Maria Isabel Perez, San Francisco, CA (US);

Jason Y. Wu, Albany, CA (US);

James David Clarkson, El Sobrante, CA (US);

Gabriel Antonio Paulius Velarde, San Leandro, CA (US);

Niloy Mukherjee, San Ramon, CA (US);

Noriyuki Sato, Hillsboro, OR (US);

Amrita Mathuriya, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Ramamoorthy Ramesh, Moraga, CA (US);

Assignee:

KEPLER COMPUTING INC., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H10B 53/30 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); H01L 28/55 (2013.01); H01L 28/60 (2013.01);
Abstract

Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.


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