The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Apr. 18, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Blandine Duriez, Brussels, BE;
Mark van Dal, Linden, BE;
Martin Christopher Holland, San Jose, CA (US);
Gerben Doornbos, Kessel-Lo, BE;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 29/775 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); B82Y 10/00 (2011.01); H01L 29/165 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); B82Y 10/00 (2013.01); H01L 21/02304 (2013.01); H01L 21/324 (2013.01); H01L 21/76802 (2013.01); H01L 21/76841 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7848 (2013.01); H01L 29/78696 (2013.01); H01L 21/823418 (2013.01); H01L 29/165 (2013.01);
Abstract
In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.