The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Dec. 22, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Hyangkeun Yoo, Icheon-si, KR;

Jae Gil Lee, Icheon-si, KR;

Se Ho Lee, Yongin-si, KR;

Assignee:

SK HYNIX INC., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H10B 51/20 (2023.01); H01L 21/28 (2006.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H10B 51/30 (2023.02);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.


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