The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Aug. 09, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Vidhya Ramachandran, Cupertino, CA (US);

Sanjay Dabral, Cupertino, CA (US);

SivaChandra Jangam, Milpitas, CA (US);

Jun Zhai, Cupertino, CA (US);

Kunzhong Hu, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/58 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 2223/5446 (2013.01);
Abstract

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.


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