The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Sep. 01, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shi Ning Ju, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Guan-Lin Chen, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 21/762 (2006.01); B82Y 10/00 (2011.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/76229 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/6681 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); B82Y 10/00 (2013.01);
Abstract

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.


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