The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Apr. 12, 2021
Applicant:

Chipbond Technology Corporation, Hsinchu, TW;

Inventors:

Yu-Chen Ma, Kaohsiung, TW;

Hsin-Hao Huang, Kaohsiung, TW;

Wen-Fu Chou, Kaohsiung, TW;

Gwo-Shyan Sheu, Kaohsiung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/118 (2013.01); H05K 1/189 (2013.01); H05K 2201/0979 (2013.01); H05K 2201/09445 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.


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