The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2023
Filed:
Jun. 04, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/1054 (2013.01); H01L 29/7843 (2013.01); H01L 29/7846 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/823892 (2013.01); H01L 27/0928 (2013.01);
Abstract
A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.