The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Jan. 03, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Jian-Ting Chen, Taichung, TW;

Yao-Ting Tsai, Taichung, TW;

Hsiu-Han Liao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H10B 41/27 (2023.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); H01L 21/823437 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.


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