The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Jul. 21, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sang Cheon Park, Hwaseong-si, KR;

Dae-Woo Kim, Seongnam-si, KR;

Hyuekjae Lee, Hwaseong-si, KR;

Taehun Kim, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01);
Abstract

A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.


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