The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Jun. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Yu Yang, Hsinchu, TW;

Po-Wei Liu, Hsinchu, TW;

Yun-Chi Wu, Hsinchu, TW;

Yu-Wen Tseng, Hsinchu, TW;

Chia-Ta Hsieh, Hsinchu, TW;

Ping-Cheng Li, Hsinchu, TW;

Tsung-Hua Yang, Hsinchu, TW;

Yu-Chun Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/74 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/743 (2013.01); H01L 23/535 (2013.01);
Abstract

A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.


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