The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2023
Filed:
Aug. 24, 2021
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Matthew David Eaton, Stow-cum-Quy, GB;
George Simon Taylor, Round Rock, TX (US);
Zhuo Li, Austin, TX (US);
James Youren, Cambridge, GB;
Ji Xu, Cambridge, GB;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 30/398 (2020.01); G06F 117/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 2117/04 (2020.01);
Abstract
Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.